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ADM1041
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VOLTAGE ERROR AMPLIFIER
This is a high gain transconductance amplifier that takes its
input from the load voltage trim stage described previously. The
amplifier requires only the output pin for loop compensation,
which typically consists of a series RC network-to-common. A
parallel resistor may be added to common to reduce the open-
loop gain and thereby provide some output voltage droop as
output current increases. The output of the amplifier is typically
connected to an emitter follower that drives an optocoupler,
which in turn controls the duty of the primary side PWM. The
emitter follower should have a high gain to minimize loading
0
0
1
2
VOLTAGE (V)
3
4
effects on the amplifier. Alternatively, an op amp voltage
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
Figure 10. Current Limit
MAIN VOLTAGE REFERENCE
A 1.5 V reference is connected to the inverting input of the
voltage error amplifier. This 1.5 V reference is the output voltage
of the soft-start circuit. Under closed-loop conditions, the
voltage at the noninverting input is also controlled to 1.5 V.
During start-up, the output voltage should be ramped up in a
linear fashion at a rate that is independent of the load current.
This is achieved by digitally ramping up the reference voltage by
using a counter and a DAC. The ramp rate is configurable via
CURRENT SENSE AMPLIFIER
This is a two-stage differential amplifier that achieves low offset
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100
1k
10k 100k
1M
10M
100M
and accuracy. The amplifier has the option to be chopped to
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100
80
BANDWIDTH
Figure 11. V CMP Transconductance
reduce offset or left as a linear amplifier without chopping.
Refer to the Register Listing for more details. Its gain may be
selected from three ranges. It is followed by a trim stage and
then by a low gain buffer stage that can be configured with a
gain of 1.0 or 2.1. The result is a total of six overlapping gain
ranges (65 to 230), one of which must be selected via the SMBus.
This gives ample adjustment to compensate for the poor initial
tolerance of the resistance wires typically used for current
sensing. It also allows selecting a higher sensitivity for better
efficiency or a lower sensitivity for better accuracy (lower offset).
The amplifier offset voltage is trimmed to zero in a once-off
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100
1k
10k 100k
1M
10M
100M
operation via the SMBus and uses a voltage controlled current
source at the output of the first gain stage. A second controlled
current source is used to trim out the additional offset due to
the mismatch of the external divider resistors. This offset trim is
dynamically adjusted according to the common-mode voltage
BANDWIDTH
Figure 12. C CMP and S CMP Transconductance
present at the top of the voltage dividers. Six ranges are selectable
according to the magnitude and polarity of this offset component.
Because the offset compensation circuit itself has some inaccu-
racies, the best overall current sense accuracy is obtained by
using more closely matched external dividers and then selecting
Rev. A | Page 21 of 64
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